Functional Modeling of Dry Etch at Semiconductor Manufacturing
Current situation
The dry etch process in semiconductor manufacturing, essential for creating intricate micro- and nanoscale structures, faces challenges due to the dual nature of its mechanisms. While chemical and mechanical etching are crucial for achieving precise feature dimensions, they can inadvertently lead to defects. Issues arise from plasma exposure, which can damage resist and sacrificial layers, producing unwanted by-products and leading to the formation of silicon-oxide or silicon-oxyfluoride particles. Additionally, excessive ion bombardment may cause material sputtering, resulting in redeposition, micromasking, residues, and underetching, all of which compromise the integrity of the etching process. The project aims to develop a functional model to better understand these interactions and optimize process parameters to mitigate defect formation.
Disadvantages
The presence of defects in the dry etch process can lead to reduced yield and increased production costs, as defective wafers may need to be reworked or discarded.
Defects caused by plasma exposure and excessive ion bombardment can compromise the precision of micro- and nanoscale structures, negatively impacting the performance and reliability of semiconductor devices.
The formation of unwanted by-products and residues can complicate the cleaning and maintenance of equipment, leading to increased downtime and operational inefficiencies.
Ideal final result
Achieve a defect-free dry etch process that maintains high yield and reduces production costs.
Gaps
Insufficient understanding of the interactions between plasma exposure and material properties, leading to defects.
Problem statement
The lack of a comprehensive model to analyze the effects of process parameters on defect formation in dry etch is hindering efforts to achieve a defect-free process and maintain high yield in semiconductor manufacturing.
Similar projects
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.