Radial CDO Non-Uniformity Causing Wafer Edge Speed Loss

Wafer final test data indicates a radial performance variation: dies closer to the wafer center tend to be faster, while dies nearer the wafer edge tend to be slower. The submitted investigation ties this pattern to a matching increase in RC-delay toward the wafer perimeter, suggesting the speed split is not random but systematic across the wafer radius. The issue is framed as a yield-loss problem with high urgency because it repeats radially across the wafer and can affect product binning and customer performance targets.

The leading explanation is that the PECVD CDO dielectric used in BEOL formation is not uniform from center to edge. The hypothesis is that the edge region experiences a different deposition environment — including gas flow, pumping, plasma sheath behavior, edge temperature, residence time, and radical concentration — because it is closer to the exhaust path. Under that condition, the CDO at the edge may become more oxide-like, denser, lower in carbon, and higher in dielectric constant, which would raise capacitance and increase RC-delay.

What is known so far is the existence of the radial trend in speed and RC-delay, plus a plausible process mechanism in the PECVD chamber. What remains uncertain is whether the dominant driver is capacitance variation alone or whether metal resistance also contributes materially, along with the exact radial profiles of thickness, carbon content, density, and dielectric constant. The investigation is therefore centered on radial process non-uniformity rather than on tuning only the average film behavior.

Symptoms

• Slower processors/dies appear more frequently near the wafer edge.
• Faster dies appear more frequently near the wafer center.
• RC-delay increases toward the wafer edge.
• There may also be higher deposition rate or different thickness at the edge, though this is not confirmed as the main issue.

Impact

• Performance variation across dies from the same wafer.
• Potential yield loss.
• Risk to binning consistency and customer performance targets.
• Recurrence appears systematic and radial rather than isolated.
• Urgency is rated high.

Affected scope

• PECVD CDO deposition for BEOL dielectric formation.
• PECVD chamber.
• Wafer edge / radial perimeter region.
• Wafer-level processor dies and the CDO low-k dielectric film.

Hypotheses

• The edge PECVD environment differs from the center due to gas flow, pumping, plasma sheath, temperature, residence time, and radical concentration.
• The CDO at the edge is over-decomposed or more heavily oxidized, making it more oxide-like and higher-k.
• The edge film may have higher deposition rate and/or different thickness, but the main issue is material property variation.
• Metal resistance may also contribute to the observed RC-delay variation.

Assumptions

• The wafer map trend reflects the underlying root cause rather than a coincidental correlation.
• The edge CDO film property change is large enough to affect device speed.
• BEOL RC-delay is a primary driver of the observed processor speed variation.

Unknowns and open questions

• Exact wafer product and process node.
• Measured k values, thickness, carbon content, porosity, and density across radius.
• Whether metal resistance contributes materially alongside capacitance.
• Which PECVD chamber settings or hardware features are currently in use.
• Magnitude of the performance and yield impact.
• What the radial profiles of CDO thickness, carbon content, density, and dielectric constant actually look like.
• Is the RC-delay increase driven mainly by capacitance or also by interconnect resistance?
• Which chamber parameters differ most between center and edge: gas ratio, RF coupling, chuck temperature, exhaust proximity, or residence time?
• Can edge compensation or multi-zone tuning flatten the radial film property profile?
• How large is the resulting speed bin split or yield impact across wafers?

Evidence

• Measurement: speed score versus wafer radius shows faster dies closer to the center and slower dies closer to the edge.
• Observation: dies from the same wafer can have different speeds, with neighboring dies also differing.
• Measurement: RC-delay increases toward the wafer edge.
• Observation: the wafer edge experiences a different process environment than the center because of gas flow, pumping, plasma, temperature, and residence-time differences.
• Observation: the edge film may become more oxide-like, denser, lower in carbon, and higher in dielectric constant.
• Other: proposed fixes include multi-zone showerhead, edge compensation ring, and edge plasma/temperature control to create intentional non-uniformity for uniform results.

Key links

• PRIZ-native investigation