The process is related to microelectronics - microchip manufacturing.
The purpose of the process is to create a SiO2 layer on the surface of a Si wafer.
Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface.
Process: The oxidation occurs on the front side and the back side of the wafer: Si (wafer) + O2 (gas within the furnace) --> SiO2 (thin film layer on the wafer surface.
The process is performed in batches of up to 150 wafers in one run.
Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer
Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Important note: In order to achieve better thermal uniformity, the furnace is built of three heaters that are managed differently according to data from a certain thermocouple (TC).
The project aims to analyze the system and process using Process Functional Modeling (PFM), create a model of the process, create a model of the failure, and generate a solution.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage