Wet etch is an important semiconductor manufacturing process used for selective material removal, surface cleaning, residue removal, and wafer-surface preparation before the next process step. It is commonly applied after lithography, dry etch, deposition, CMP, or implantation to remove unwanted films, native oxides, polymers, particles, metallic contamination, or process residues.
The main purpose of wet etch is to remove the target material or contamination while preserving required structures, dimensions, surface quality, and material selectivity. The process must provide a stable etch rate, good within-wafer uniformity, low particle adders, complete residue removal, and repeatable drying performance.
In single-wafer wet etch equipment, one wafer is processed at a time on a rotating chuck inside a plastic process chamber. The wafer is clamped or supported by lift pins and rotated during processing. One or more independent movable nozzles dispense chemistry or DI water onto the wafer surface. Each nozzle may be dedicated to a specific chemical, rinse, or drying function. Wafer rotation spreads the liquid across the surface, supports mass transport, and helps remove reaction products. After chemical processing, the wafer is rinsed with DI water and dried, typically using high-speed spin drying and nitrogen flow. Spent chemistry, rinse water, removed residues, and particles are collected through the bowl, drain, and exhaust systems.
Although wet etch is often considered a cleaning or correction process, it can also create defects. Typical problems include incomplete residue removal, particle redeposition, watermarks, nonuniform etch rate, local underetch or overetch, surface roughening, corrosion, pattern damage, chemical residues, poor drying, and contamination from chemistry, chamber parts, nozzles, drains, or maintenance activities.
These defects directly impact manufacturing performance. Residues and particles can cause electrical opens or shorts, poor contact formation, leakage, reliability failures, and yield loss. Nonuniform etching or overetch can damage critical structures and reduce process margin. Additional rework, inspection, tool cleaning, and recipe tuning increase cycle time, reduce throughput, and increase manufacturing cost.
Wet etch problems may occur continuously at a low background level or appear as excursions after recipe changes, chemical-batch changes, filter changes, nozzle maintenance, chamber cleaning, drain issues, long idle time, or processing of difficult product layers. The occurrence pattern should be captured during the project by reviewing defect maps, particle trends, metrology data, tool history, lot history, and maintenance records.
Important process and equipment parameters to include in the Functional Model are chemical composition and concentration, temperature, dispense flow rate, dispense time, nozzle position, nozzle scan path, wafer rotation speed, rinse time, drying speed, nitrogen flow, chamber humidity, drain efficiency, filter condition, chemical age, and maintenance history.
The goal of this project is to build a Functional Model of the wet etch system, identify useful and harmful interactions between the wafer, chemistry, residues, particles, liquid flow, equipment components, and process parameters, and reveal the main mechanisms responsible for defect formation. The model will help generate practical directions for improving etch performance, selectivity, wafer cleanliness, throughput, and process stability while reducing residues and particles.
A typical wet etch process chamber is shown below:
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates the nonuniform erosion of an expensive Ta sputtering target during Ta/TaN PVD. A deep racetrack groove forces target replacement while a significant amount of tantalum remains unused. Using PRIZ problem-solving tools, the project explores the system’s functions, identifies the root causes of localized erosion, and develops ways to improve target utilization without reducing deposition rate or production throughput.