In Ta PVD, the Ta/TaN sputtering target is eroding non-uniformly and developing a deep racetrack groove. The problem is not that the target is being used up evenly and then naturally retired; it is that the target must be replaced while a significant amount of Ta remains. That makes the issue primarily one of consumable cost and target utilization, with the erosion concentrated in a narrow region of the target surface.
The team’s current understanding points to the magnetron magnetic-field configuration as the main driver. The field traps electrons near the target surface, increases plasma density, and improves sputtering efficiency, but it also localizes sputtering in the racetrack area. In other words, the same mechanism that helps deposit the Ta barrier efficiently also creates the deep erosion groove that shortens usable target life. Recipe tuning has been tried: lowering the deposition rate slightly changed the erosion profile, but the improvement was small, and the throughput penalty was judged unacceptable.
This issue appears in the Ta PVD process used to deposit tantalum, and sometimes tantalum nitride, as a barrier before Cu metallization. The barrier film is needed to prevent Cu diffusion into the SiO₂-based dielectric and protect interconnect reliability, so the process itself is important to the product. What is still uncertain is how far the erosion problem extends beyond cost: the candidate notes do not confirm whether there are current wafer defects, particle issues, film nonuniformity, or shield damage. The open question is whether this is mainly an economic/utilization problem or whether it is also affecting yield and chamber health.
Captured from investigation notes
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.