Mr. Beliakou

Wafer final test data indicates a radial performance variation: dies closer to the wafer center tend to be faster, while dies nearer the wafer edge tend to be slower. The submitted investigation ties this pattern to a matching increase in RC-delay toward the wafer perimeter, suggesting the speed split is not random but systematic across the wafer radius. The issue is framed as a yield-loss problem with high urgency because it repeats radially across the wafer and can affect product binning and customer performance targets.
The leading explanation is that the PECVD CDO dielectric used in BEOL formation is not uniform from center to edge. The hypothesis is that the edge region experiences a different deposition environment — including gas flow, pumping, plasma sheath behavior, edge temperature, residence time, and radical concentration — because it is closer to the exhaust path. Under that condition, the CDO at the edge may become more oxide-like, denser, lower in carbon, and higher in dielectric constant, which would raise capacitance and increase RC-delay.
What is known so far is the existence of the radial trend in speed and RC-delay, plus a plausible process mechanism in the PECVD chamber. What remains uncertain is whether the dominant driver is capacitance variation alone or whether metal resistance also contributes materially, along with the exact radial profiles of thickness, carbon content, density, and dielectric constant. The investigation is therefore centered on radial process non-uniformity rather than on tuning only the average film behavior.
<h2>Symptoms</h2>
<ul>
<li>Slower processors/dies appear more frequently near the wafer edge.</li>
<li>Faster dies appear more frequently near the wafer center.</li>
<li>RC-delay increases toward the wafer edge.</li>
<li>There may also be higher deposition rate or different thickness at the edge, though this is not confirmed as the main issue.</li>
</ul>
<h2>Impact</h2>
<ul>
<li>Performance variation across dies from the same wafer.</li>
<li>Potential yield loss.</li>
<li>Risk to binning consistency and customer performance targets.</li>
<li>Recurrence appears systematic and radial rather than isolated.</li>
<li>Urgency is rated high.</li>
</ul>
<h2>Affected scope</h2>
<ul>
<li>PECVD CDO deposition for BEOL dielectric formation.</li>
<li>PECVD chamber.</li>
<li>Wafer edge / radial perimeter region.</li>
<li>Wafer-level processor dies and the CDO low-k dielectric film.</li>
</ul>
<h2>Hypotheses</h2>
<ul>
<li>The edge PECVD environment differs from the center due to gas flow, pumping, plasma sheath, temperature, residence time, and radical concentration.</li>
<li>The CDO at the edge is over-decomposed or more heavily oxidized, making it more oxide-like and higher-k.</li>
<li>The edge film may have higher deposition rate and/or different thickness, but the main issue is material property variation.</li>
<li>Metal resistance may also contribute to the observed RC-delay variation.</li>
</ul>
<h2>Assumptions</h2>
<ul>
<li>The wafer map trend reflects the underlying root cause rather than a coincidental correlation.</li>
<li>The edge CDO film property change is large enough to affect device speed.</li>
<li>BEOL RC-delay is a primary driver of the observed processor speed variation.</li>
</ul>
<h2>Unknowns and open questions</h2>
<ul>
<li>Exact wafer product and process node.</li>
<li>Measured k values, thickness, carbon content, porosity, and density across radius.</li>
<li>Whether metal resistance contributes materially alongside capacitance.</li>
<li>Which PECVD chamber settings or hardware features are currently in use.</li>
<li>Magnitude of the performance and yield impact.</li>
<li>What the radial profiles of CDO thickness, carbon content, density, and dielectric constant actually look like.</li>
<li>Is the RC-delay increase driven mainly by capacitance or also by interconnect resistance?</li>
<li>Which chamber parameters differ most between center and edge: gas ratio, RF coupling, chuck temperature, exhaust proximity, or residence time?</li>
<li>Can edge compensation or multi-zone tuning flatten the radial film property profile?</li>
<li>How large is the resulting speed bin split or yield impact across wafers?</li>
</ul>
<h2>Evidence</h2>
<ul>
<li>Measurement: speed score versus wafer radius shows faster dies closer to the center and slower dies closer to the edge.</li>
<li>Observation: dies from the same wafer can have different speeds, with neighboring dies also differing.</li>
<li>Measurement: RC-delay increases toward the wafer edge.</li>
<li>Observation: the wafer edge experiences a different process environment than the center because of gas flow, pumping, plasma, temperature, and residence-time differences.</li>
<li>Observation: the edge film may become more oxide-like, denser, lower in carbon, and higher in dielectric constant.</li>
<li>Other: proposed fixes include multi-zone showerhead, edge compensation ring, and edge plasma/temperature control to create intentional non-uniformity for uniform results.</li>
</ul>
<h2>Key links</h2>
<ul>
<li><a href="source:priznative">PRIZ-native investigation</a></li>
</ul>

<h2>Showerhead radial compensation</h2>Your idea about different hole sizes is very relevant.The showerhead is not only a gas distributor. In PECVD, it also influences plasma structure, local precursor delivery, oxidant delivery, residence time, and sometimes RF coupling. Patents and PECVD studies show that showerhead hole pattern, hole density, radial zones, and edge-flow design are used exactly to improve center-to-edge film uniformity and film propertiesBest concept:<blockquote>Multi-zone showerhead: center zone and edge zone with independently controlled flows.</blockquote>For example:<ol><li data-list="bullet">Center zone: normal CDO precursor + oxidant ratio</li><li data-list="bullet">Edge zone: slightly higher carbon precursor / lower oxidant ratio</li><li data-list="bullet">Outer ring purge: inert gas curtain to control edge plasma and residence time</li></ol>This is better than changing only the global precursor ratio.

<h2>Post-treatment compensation</h2>For porous CDO, UV cure or plasma cure can also create radial k variation.If edge k increases after cure, not during deposition, then the compensation should be in the cure:<ol><li data-list="bullet">radial UV intensity correction,</li><li data-list="bullet">wafer rotation during cure,</li><li data-list="bullet">edge masking / reduced edge exposure,</li><li data-list="bullet">temperature compensation during cure,</li><li data-list="bullet">optimized cure time to avoid edge over-densification.</li></ol>So first we need to know:<blockquote>Is edge k already high after deposition, or only after cure / integration?</blockquote>This is critical.

<h2>Pressure, gap, and pumping compensation</h2>Edge k can also come from different residence time and exhaust behavior.Try:<ol><li data-list="bullet">change chamber pressure,</li><li data-list="bullet">change showerhead-to-wafer spacing,</li><li data-list="bullet">tune throttle valve/pumping symmetry,</li><li data-list="bullet">add flow straighteners,</li><li data-list="bullet">use symmetric exhaust or compensated edge exhaust,</li><li data-list="bullet">reduce lateral gas flow along the wafer surface.</li></ol>A useful principle:<blockquote>If the edge composition is different, check whether the edge gas composition is different before it reaches the surface.</blockquote>

<h2>Chemistry ratio compensation: carbon/oxygen balance</h2>If edge k is high, one likely mechanism is:<blockquote>Edge receives relatively more oxidizing environment → lower carbon content → denser Si–O network → higher k</blockquote>So compensation could be:<ol><li data-list="bullet">lower O₂ / N₂O / CO₂ fraction globally or locally,</li><li data-list="bullet">increase organosilicon precursor at edge,</li><li data-list="bullet">increase porogen or carbon-rich precursor at edge,</li><li data-list="bullet">reduce oxidant dissociation near edge,</li><li data-list="bullet">use a less oxygen-aggressive chemistry.</li></ol>But global change may damage center performance. Therefore:<blockquote>Local chemistry compensation is better than global chemistry compensation.</blockquote>

<h2>RF/plasma radial compensation</h2>The edge often sees a different plasma sheath and radical flux. If the edge plasma is more aggressive, it may increase oxidation, remove carbon-containing groups, densify the film, or damage porous CDO.Possible directions:<ol><li data-list="bullet">tune RF frequency/power split,</li><li data-list="bullet">change electrode spacing,</li><li data-list="bullet">redesign edge ring,</li><li data-list="bullet">add plasma confinement ring,</li><li data-list="bullet">adjust showerhead-to-wafer gap,</li><li data-list="bullet">use pulsed plasma,</li><li data-list="bullet">reduce ion bombardment during the carbon-sensitive part of deposition.</li></ol>A very good process concept:<blockquote>Separate deposition and densification.</blockquote><blockquote> First deposit carbon-rich low-k film gently. Then apply controlled UV / plasma treatment more uniformly.</blockquote>This reduces the chance that the edge is over-treated during deposition.

<h2>Radial temperature compensation</h2>If the edge is hotter, the CDO may become denser, more oxide-like, less porous, and therefore higher-k.Possible solutions:<ol><li data-list="bullet">improve ESC thermal uniformity,</li><li data-list="bullet">tune backside He cooling zones,</li><li data-list="bullet">reduce edge-ring heating,</li><li data-list="bullet">modify edge ring material/emissivity,</li><li data-list="bullet">add multi-zone chuck control,</li><li data-list="bullet">reduce plasma heating near the edge.</li></ol>For CDO, temperature is important because it can affect carbon incorporation, densification, porogen behavior, moisture sensitivity, and final k.Strong idea:<blockquote>If edge k is higher because edge film is denser, compensate by lowering edge temperature or reducing edge plasma power density.</blockquote>

<h2>Edge gas ring/compensation ring</h2>A very practical concept is an independent edge gas ring around the showerhead or chamber wall.It could supply:<ol><li data-list="bullet">inert gas to dilute edge plasma,</li><li data-list="bullet">carbon-containing precursor to compensate carbon depletion,</li><li data-list="bullet">lower oxidant concentration near the edge,</li><li data-list="bullet">purge gas to reduce edge residence time.</li></ol>This gives a powerful control knob:<blockquote>Use the edge ring to tune only the last 10–20 mm of the wafer radius.</blockquote>This is useful because the edge problem is often localized.

<h2>Larger showerhead / extended edge coverage</h2>Increasing showerhead diameter can help if the current showerhead creates edge starvation or edge boundary distortion.If the gas distribution ends too close to the wafer edge, the edge region behaves like a boundary zone rather than a normal deposition zone. A larger showerhead, or an edge-compensated faceplate, can make the wafer edge “feel” more like the wafer center.Concept:<blockquote>Do not allow the wafer edge to see the end of the gas-distribution system. Move the gas-distribution boundary outside the wafer.</blockquote>This can reduce radial discontinuity in precursor flux, oxidant flux, and plasma density.

This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge.

The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂.

As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed.

The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.

Radial CDO Non-Uniformity Causing Wafer Edge Speed Loss

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Radial CDO Non-Uniformity Causing Wafer Edge Speed Loss

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