Time-depending yield degradation at microchip manufacturing
Manage the process flow to ensure the lowest dwelling time between the process end and the final test.
A special procedure of lots management was created and used as a temporary solution. Such a procedure is difficult, costly, and does not bring significant success. Rejected
Since CuF2 is water-soluble stuff, wash the wafers in water before running the final test
Washing wafers with water prior to the final test gave excellent results. The washing operation was approved and implemented as a long-term temporary solution until we got the final solution.
Eliminate the dry etch operation and replace it with the wet etch with the diluted-HF solution.
The main idea was to create the required structure using only the wet processes:
Set up process containing wet operations only.
1 operation - Cu removal with H2SO4 + H2O2 (Chem 1)
2 operation - Ti removal with diluted HF (Chem 2)
The process was completed and showed negative results - too deep an undercut is created due to interaction between HF and Ti under the Cu bumps:
Additional investigation is needed. Use 40 Inventive Principles to find a creative solution
Principle #22 - Blessing in disguise (Turn Lemons into Lemonade) seems to be very relevant
Eliminate primary harmful factors by following harmful factors.
The main idea is that we can eliminate undercut by two ways: Not to make undercut or remove overcut:
We can use Chem 1 twice to eliminate the undercut - add a makeup process:
Slightly reduce the Cu removal time with Chem 1, perform Ti removal with Chem 2, makeup - remove the overcut of Cu with Chem 1 for the ti,e remaining from the budget of the Cu removal.
Similar projects
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)