Silicon wafers are processed to create hundreds of dies. During manufacturing, transistors and interconnections are made. At the end of the processing, the upper layers and bumps are fabricated outer connections of a die.
A typical processed wafer is shown below:
Bumps made of the Cooper are located on the very top of each die. Typical bumps are shown below:
The bumps are used for the final test of all dies. The final test is an electrical test that is performed using prob-cards equipped with micro pins. Micro pins touch the bumps that allow them to perform electrical tests: send signals and receive results. Only good dies are taken for the packaging. All dies that fail the test will be scrapped. The process yield depends on the amount of "good" and "bad" dies.
It was revealed that the time between the end of the process and the final test impacts the yield. The longer the dwelling the more dies fail the final test. If the dwelling exceeds hundreds of hours the amount of failed dies becomes dramatically high, which results in the scrapping of the whole wafer.
Time-dependence yield degradation is illustrated in the picture below. Failed dies are marked by blue an red colors.
The end of the process is shown in the picture below:
The bumps are built from Cu on the top of the dielectric layer. Ti thin layer is used to improve the adhesion of the Cu to the dielectric material. The purpose of the operations shown above is to disconnect the bumps.
The process integrates both wet etch and plasma etch operations.
Chem 1 - is the mixture of H2SO4 + H2O2 - classical solution to remove Cu. Chem 1 does not interact with Ti.
Dry etch of Ti is performed with fluorine-containing gas that removes Ti and does not remove Cu.
Chem 2 - is the HF-diluted solution that dissolves Ti and does not interact with Cu and the dielectric material.
The time depending dies degradation is observed.
TRADITIONAL APPROACH
The main reason is an oxidation of the Cu - Proposed solution - to keep the wafers in an inert atmosphere.
This is the wrong concept: even oxidized Cu remains conductive, the experiments with an inner atmosphere did not show any improvements.
The managerial problem solution is to avoid dwelling between the end of the process and the final test: plan processing and perform the final test just after processing.
Applying such a solution increases production costs and is not always viable.
The project aims to analyze the phenomenon and find a creative solution.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)