Chemical Mechanical Planarization (CMP) is a critical semiconductor manufacturing process used to remove excess material and create a flat wafer surface between fabrication steps. Planarity is essential because uneven topography can prevent accurate lithography, reliable interconnect formation, and successful integration of subsequent layers.
During copper CMP, the wafer is pressed face-down against a rotating polishing pad while slurry is supplied to the contact area. The slurry typically contains water, chemical additives, abrasive particles, and hydrogen peroxide as an oxidizer. Hydrogen peroxide reacts with the copper surface and forms an oxide layer, which is then removed by the polishing pad and abrasive particles.
The current copper removal rate is relatively low, which increases process time and limits equipment throughput. A common attempt to accelerate the process is to increase the H₂O₂ concentration in the slurry. However, engineers have found that this approach is effective only up to a certain concentration. Above that level, the Cu removal rate no longer increases and may decrease.
The purpose of this project is to understand the mechanism limiting the Cu removal rate and identify effective ways to increase CMP productivity without compromising process quality, uniformity, or wafer reliability.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.
This project investigates the nonuniform erosion of an expensive Ta sputtering target during Ta/TaN PVD. A deep racetrack groove forces target replacement while a significant amount of tantalum remains unused. Using PRIZ problem-solving tools, the project explores the system’s functions, identifies the root causes of localized erosion, and develops ways to improve target utilization without reducing deposition rate or production throughput.