Chemical Mechanical Planarization (CMP) is a critical semiconductor manufacturing process used to remove excess material and create a flat wafer surface between fabrication steps. Planarity is essential because uneven topography can prevent accurate lithography, reliable interconnect formation, and successful integration of subsequent layers.
During copper CMP, the wafer is pressed face-down against a rotating polishing pad while slurry is supplied to the contact area. The slurry typically contains water, chemical additives, abrasive particles, and hydrogen peroxide as an oxidizer. Hydrogen peroxide reacts with the copper surface and forms an oxide layer, which is then removed by the polishing pad and abrasive particles.
The current copper removal rate is relatively low, which increases process time and limits equipment throughput. A common attempt to accelerate the process is to increase the H₂O₂ concentration in the slurry. However, engineers have found that this approach is effective only up to a certain concentration. Above that level, the Cu removal rate no longer increases and may decrease.
The purpose of this project is to understand the mechanism limiting the Cu removal rate and identify effective ways to increase CMP productivity without compromising process quality, uniformity, or wafer reliability.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)