Increase the removal rate of Cu at CMP
Current situation
The Chemical Mechanical Planarization (CMP) process is essential for achieving a flat wafer surface in semiconductor manufacturing, as uneven topography can hinder subsequent fabrication steps. Currently, the copper removal rate during CMP is insufficient, resulting in longer process times and reduced equipment throughput. While increasing the concentration of hydrogen peroxide in the slurry is a common strategy to enhance the removal rate, it has been observed that this approach yields benefits only up to a certain threshold, beyond which the removal rate may stagnate or even decline. The project aims to investigate the underlying mechanisms affecting the copper removal rate and to discover effective strategies for improving CMP productivity while maintaining quality and reliability.
Disadvantages
Insufficient copper removal rate leads to longer process times, which can result in increased production costs and reduced overall efficiency in the manufacturing process.
Reduced equipment throughput due to prolonged CMP processes can cause bottlenecks in the production line, delaying the delivery of finished products to customers and potentially impacting customer satisfaction.
Relying solely on increasing hydrogen peroxide concentration may not yield consistent results, leading to variability in the removal rate and potentially compromising the quality and reliability of the final semiconductor products.
Ideal final result
Reduce the average CMP process time by Y% through optimized parameters and techniques, ensuring high-quality wafer surfaces.
Gaps
Limited understanding of the underlying mechanisms affecting the copper removal rate during CMP.
Current reliance on hydrogen peroxide concentration does not provide consistent improvements in removal rate.
Insufficient optimization of other slurry components and process parameters that could enhance the copper removal rate.
Problem statement
The current copper removal rate during CMP is insufficient, leading to longer process times and reduced equipment throughput, necessitating a deeper understanding of the underlying mechanisms and alternative optimization strategies.
Similar projects
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.