The model shows that increasing H₂O₂ concentration alone cannot continuously increase the Cu removal rate. At high peroxide concentration, copper is oxidized rapidly and a thick, continuous Cu₂O/CuO layer forms. Because this oxide occupies about 1.7–1.8 times the volume of the consumed copper, it grows quickly, passivates the surface, and becomes the new barrier to removal.
The winning solution is therefore to balance chemical oxidation with mechanical removal. When the oxidation rate is increased, the mechanical part of the CMP process must also be strengthened. This can be achieved by increasing pad speed, optimizing pressure, increasing abrasive-particle concentration, or improving pad conditioning and slurry transport.
The key principle is:
Do not increase only the oxidation rate. Increase the capacity to remove the oxide at the same time.
A higher H₂O₂ concentration is useful only when the pad, abrasives, and process conditions can remove the oxide layer at a matching rate. The most effective solution is not the maximum peroxide concentration, but the optimum combination of chemical oxidation and mechanical oxide removal.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)