Wafer breakage within the flash heating system:
The flash heating with the upper lamp created the gradient of the temperature of the air. The fast-changing of temperature results in the wind (tornado) formation that leads to the movement of the wafer. The moving of the wafer may result in a mechanical hit followed by the wafer breakage.
Wafer breakage occurs at flash heating
Run additional wafers to compensate for the broken wafers
A mechanical hit occurs
Redesign the pedestal or add a ring having no "walls" - no parts that the wafer can hit
Wafer moves due to air pressure difference appearing due to flash heating
Keep the wafer static - no movements at all (vacuum keeper?)
The pedestal has a special configuration: the wafer moves and can get a mechanical hit
Redesign the pedestal to exclude a mechanical hit
How wafer breakage occurs while the flash heating process:
Effective
Ineffective
Basic functions
Components
Supersystems
The main conclusion is that we need to exclude either movement of the wafer or vertical solid parts that the wafer can hit
If | we exclude the wafer movement |
---|---|
Then | no breakage will occur due to a mechanical hit |
But | The thermal stress could appear and affect the parameters of the product or even result in breakage due to thermal stress |
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.