Wafer breakage within the flash heating system:
The flash heating with the upper lamp created the gradient of the temperature of the air. The fast-changing of temperature results in the wind (tornado) formation that leads to the movement of the wafer. The moving of the wafer may result in a mechanical hit followed by the wafer breakage.
Wafer breakage occurs at flash heating
Run additional wafers to compensate for the broken wafers
A mechanical hit occurs
Redesign the pedestal or add a ring having no "walls" - no parts that the wafer can hit
Wafer moves due to air pressure difference appearing due to flash heating
Fixate the wafer - no movements at all (vacuum chuck?)
The pedestal has a special configuration: the wafer moves and can get a mechanical hit
Redesign the pedestal to exclude a mechanical hit
How wafer breakage occurs while the flash heating process:
Effective
Ineffective
Basic functions
Components
Supersystems
Pedestal | 8 |
Low lamp | 6 |
Bumps | 4 |
Centering pins | 4 24 |
Upper light (flash) | 4 |
Atmosphere (N2) | 12 |
Air | 8 |
The main conclusion is that we need to exclude either movement of the wafer or vertical solid parts that the wafer can hit
If | Centering pins remains unchanged |
|---|---|
Then | Centering pins Hold Wafer |
But | Centering pins Stops Wafer |
If | we exclude the wafer movement |
|---|---|
Then | no breakage will occur due to a mechanical hit |
But | The thermal stress could appear and affect the parameters of the product or even result in breakage due to thermal stress |
Wafers break due to flash heating
Let's analyze the possibility of a mechanical hit during the flash heating process
Wafer got a mechanical hit during the flash heating process
Mechanical hit of the wafer with centring pins
Redesign centering pins with flexible, low-friction polymer coatings or spring-loaded tips that absorb minor impacts and allow self-centering without causing damage during wafer movement.
The wafer should move during the flash heating process
Keep the wafer against movement
Nitrogen gas moves and moves the wafer
Redesign the quartz pedestal with additional low-profile support ridges or pins positioned to provide lateral stability to the wafer, preventing displacement from gas flows while maintaining uniform light exposure.
Rapid thermal expansion of chamber gases inducing convective currents
Process in a vacuum or at least in low pressure
Different temperatures cause different pressures of nitrogen
Add the same flight on the bottom to get the same temperature
Flash heating is needed for implant ions activation
Integrate in-situ plasma-assisted activation during implantation to partially activate ions, reducing the reliance on subsequent high-temperature flash heating steps.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.