The Process Functional Modeling of the SiO2 thin film layer creation has revealed problems as follows:
Based on the concept of moving wafers, let's describe the models of the failures of bottom zone wafers' thickness sigma (thickness standard deviation)
Model 1. The loading of the boat with wafers causes overheating at the bottom zone of the furnace
During loading the wafers into the furnace (that is at 300C), the cold wafers "cool" the bottom thermocouple (TC) that resulting in strong overheating of the bottom zone.
Model 2. The Loading of the boat with wafers causes the presence of air residue in the bottom zone of the wafer.
During the loading of the wafers, the N2 flow mainly removes the air from the furnace, but some residual amount may remain and it will be collected in the bottom zone of the furnace. As a result, the wafers in the bottom zone will start oxidation earlier and will receive more O2.
Model 3. The unloading of the wafers from the furnace will result in additional uncontrolled oxidation on the bottom zone wafers
During the unloading of the boat with wafers, the bottom wafers expose to the atmosphere first. They have a higher temperature when exposed to the air and they keep the temperature longer because they are placed close to the massive bottom flange.
Possible solutions:
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.
This project investigates the nonuniform erosion of an expensive Ta sputtering target during Ta/TaN PVD. A deep racetrack groove forces target replacement while a significant amount of tantalum remains unused. Using PRIZ problem-solving tools, the project explores the system’s functions, identifies the root causes of localized erosion, and develops ways to improve target utilization without reducing deposition rate or production throughput.