SiO2 thin film creation in Diffusion furnace - Process Functional Modeling
Current situation
The thickness standard deviation (sigma) of SiO2 thin layer on the silicon wafer is high
Disadvantages
The high standard deviation of the SiO2 thin layer on the silicon wafer is bad because it indicates that the layer is not uniform and that there are significant variations in the thickness across the wafer. This can lead to issues with the performance of the device and potential reliability issues.
Ideal final result
Use Process Functional Modeling (PFM) to create a model of the process and a model of the failure. Generate a solution
Gaps
We do not understand the reason for the different processes in the different zones
Problem statement
The process conditions are different in the different zones of the furnace. Wafers in the low zone show worse performance.
Similar projects
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
The project was dedicated to production yield improvement in microchip manufacturing. The bumps are created on the top of a wafer and used for the final test of all dies. Only good dies are taken for the packaging. All dies that fail the test will be scrapped. The process yield depends on the amount of "good" and "bad" dies. It was revealed that in some cases, the time between the end of the process and the final test impacts the yield. The longer the dwelling, the more dies fail the final test. If the dwelling exceeds hundreds of hours, the amount of failed dies becomes dramatically high, which results in the scrapping of the whole wafer. The problem was analyzed and solved.
