Mr. Beliakou

To ensure a small gap between the metal line and ILD. It could be made in different ways, such as using soluble Barriers, we can use a difference in temperature expansion coefficients, etc.

Use ILD with non-uniform density. Actually, we need high density of the material to prevent diffusion of Cu in to ILD

Use silicide passivation instead of a thick Ta barrier layer.

The cleaning solution dissolves the residue, but the contaminated solution remains on the wafer and should be removed by the wafer rotation. The rotation of the wafer results in the removal of the cleaning solution. I would propose to apply "Other way around" principle. Instead of pour out the solution on the rotating wafer, we could rotate the wafer (face down) in the bath of the solution. It gives a better possibility of managing the temperature and renovating the cleaning solution on the wafer surface.

Another idea regarding Step 4 - Via Patterning simplification:Why do we need to develop exposed PR at all? Exposed PR is removed by an aqueous solution, meaning it can be removed by plasma. So, the idea is to apply plasma etch directly after exposure.

Regarding the Step 4 - Photo Lithography (PL) operation simplification: Why do we develop within the costly PL equipment? Developing the exposed resist is just a wet etch/clean process that can be performed with regular cheap wet cleaning equipment.

In Step 3 - Sacrificial Light Absorbing Layer deposition - use hot air for the material solidification on the wafer during the Spinon process. This will allow the termination of the furnace and additional movements of the wafer. The high pressure above the rotating wafer will prevent the material from contamination.

Air daps also prevent the formation of voids within the metal via a metal line - we already have voids. Very strong Cu-electromigration might slightly affect the surface of the via and metal line, but the voids will not be formed within the metal.

Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly.

In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges.

This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.

Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)

Projects related to innovations and problem solving in the microchip manufacturing

Optimizing IC Interconnection: A Functional Approach to Innovation

The internal or external contour or profile of a component or system as required for ergonomic and function rather than aesthetic reasons

Shape

No diffusion of Cu or voids formation due to electromigration effect - Metal line remains unchanged

Local quality

Merging

Pneumatics or hydraulics

Parameter changes

Version: Basic version, Component: Barrier - top layer

Loss or waste of elements of a system or its surroundings – substances, materials, sub-systems, products, fields, etc.  Can be partial or complete, permanent or temporary.

Loss of substance

The barrier takes the volume of the via and trench therefore, the volume of the metal via and metal line becomes smaller, reducing the conductivity of the line and affecting the current as a product

The nozzle directs the solution to the wafer to dissolve the residue

Segmentation

Component: Nozzle

This parameter is designed as a catch-all for any form of inefficiency internal to or around a system that manifests as a harmful effect on something around the system.  Can also mean any form of pollutant or environmental emission generated by a system or object.  This is a derivative of the 'loss of substance' definition above, the focus however is on "harmful emissions" this aspect is on the production of chemicals, etc. that was not one of the original substances contained within the system.

Object generated harmful factors

The cleaning solution, together with the dissolved residue remains on the wafer and should be removed by the wafer rotation

Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)

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