Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)
Material waste, including silicon and other raw materials, is a significant issue in semiconductor fabrication. Developing strategies for better material utilization and recycling is key to minimizing waste and reducing costs. The paradox is that highly sophisticated semiconductor devices are often produced through relatively simple methods, leading to lengthy processing times and inflated production costs, which ultimately increase the price of the final product.
This project aims to conduct a Functional Analysis of IC interconnection (BEOL) and a Process Functional Analysis of single-layer manufacturing. We believe this analysis will help us gain a deeper understanding of the process and uncover the most promising directions for innovation.
The project will proceed in two steps:
- System Functional Model: We will create a functional model of the interconnection components to better understand their roles and rank them based on functionality and potential problems. This analysis will help us understand the functionality of each component in the interconnection layer, as shown in the provided sketch.
- Process Functional Model: We will model and analyze the typical process of forming an additional interconnection layer on top of the one shown in the diagram below. Through Process Functional Modeling, we aim to examine the process in detail, identify the operations that add value to the product, and differentiate those that do not contribute to product value.
Both analyses will provide critical insights that can inform strategies for innovative improvements and cost reduction.
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