SiO2 thin film creation in Diffusion furnace - Process Functional Modeling

Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.

Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage

Copper electroplating is essential for forming advanced semiconductor interconnects, yet radial thickness non-uniformity remains a costly challenge. Thicker deposition at the wafer edge and thinner copper at the center force manufacturers to rely on overplating and CMP compensation, increasing material waste and process cost. Using the PRIZ Platform, this project reveals that the true amplification mechanism lies in operating within a kinetically controlled regime, where small voltage variations caused by seed-layer resistance produce large thickness deviations. By shifting the process closer to diffusion-controlled behavior and reducing sensitivity to voltage fluctuations, uniform deposition can be achieved intrinsically — enabling thinner seed layers, reduced overplating, lower CMP burden, and overall cost reduction.