Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)

We need to create a Functional Model of IC Interconnection to understand and learn the functional and problem ranks of all components.

We will take one metal layer created above the layer below.

The purpose of the IC interconnection is to electrically connect the metal in the layer below to the metal line above. Therefore, the system's product would be Current.

The challenges are as follows:

We need a dielectric material (ILD) to be able to keep the metal line mechanically and separated electrically

ILD - Interlayer dielectric that is typically built of SiO2 or modified SiO2

The metal lines and via are made from Cu

Cu diffuses through the ILD, resulting in shortening - the creation of electrical contacts through ILD

The barrier (typically Ta) is used for preventing Cu diffusion into ILD within the layer

Etch stop layer (typically Si3N4, SiC) aims to prevent Cu diffusion to ILD on the upper layer

Cu is affected by the electromigration effect; therefore, the bottom Barrier that separates the top of the via from the metal at the low layer helps to prevent the formation of huge voids due to Cu electromigration from layer to layer

During the Functional Modeling, we need to take into account the RC-delay that affects the signal and should be as low as possible. RC-delay = R X C where R is the total resistivity of metal layers, and Vias and C is the total capacitance of vertical and horizontal gaps of dielectrics located between metal lines. The resistivity of the metal lines and metal vias should be as low as possible; the Dielectric permittivity of dielectric layers should be as low as possible.

The interconnection part is shown below:

Let's start to create a Functional Model.

The next step is to analyze the manufacturing process of the IC interconnection layer.

Generally, we need to process the structure:

To the structure:

Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.

Let's start, go to the "Model"

We need to complete 13 sequential operations to create a metal layer.

Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.

A typical reasonable process flow is shown below:

Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"

1 Step is the transformation from the structure:

To the structure:

The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.

The Etch Stop layer deposition is usually performed by the CVD method.

The operation aims to create the Etch Stop layer therefore, the product is the "Etch Stop Layer"

2 Step is the deposition of the ILD layer - a transformation from structure:

To structure:

ILD is typically built of SiO2 or modified SiO2 for the reduction of dielectric permittivity. The Electric permittivity reduction is typically achieved by the creation pores and dipping with C (in the form of methyl), Fluorine

ILD deposition is typically made by the CVD process, where gaseous components are converted into a thin solid film due to the process in plasma.

The operation aims to deposit ILD; therefore, the product (target) of the step is ILD.

3 Step is the deposition of the Sacrificial light-absorbing Layer (SLAL). The main purpose of this layer is to absorb the light during Photolithography and prevent the formation of a standing wave due to the interference of initial reflected light.

The structure:

Should be converted to the structure:

The layer is typically deposited by a spin-on procedure similar to the deposition of a photoresist.

The operation aims to deposit SLAL; therefore, the product (target) of the operation is SLAL.

4th Step is the wafer patterning using Photolithography (PL). PL is a preparation for the next step, which is Dry Etch (Plasma Etch). The purpose of the operation is to deposit the Photo Resist (PR) and create a pattern: the areas that are covered with the PR will not be affected by the Plasma etch, and opened areas will be etched by plasma.

Incoming structure:

Outcoming structure after the PL process should be as follows:

This step creates the pattern for Via etch only. The PL process generally consists of three sequential parts: deposition of the Photo Resist (PR), Exposure - optical exposing of the PR through the special mask, and Development - chemical removal of the exposed part of the PR; unexposed parts will remain on the wafer. (In the case of "negative resist, "the effect is the opposite - exposed parts will remain, while unexposed parts will be removed at the development).

The operation aims to create a patterned photoresist; therefore, its product (target) is Via Patterned PR.

5th Step is to etch a Via according to the pattern that was made at the previous step - Via Photo Lithography. The etch is performed with plasma on the all surface of the wafer. The open parts will be etched, while the parts that are covered with the Photoresist (PR) will remain unchanged. The wafer is placed on the chuck, kept with static electricity and treated with plasma containing the ions and/or radicals to be able to convert the ILD in to the gas. Typically, the plasma contains fluorine that converts silicon oxide to gaseous silicon tetrafluoride.

Incoming structure:

Outcoming structure:

This step is a productive operation that provides irreversible changes and increases the value of the product.

The operation aims to create a Via within the ILD according to the patterned resist on the wafer; therefore, its product (target) is a Via.