Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)

We need to create a Functional Model of IC Interconnection to understand and learn the functional and problem ranks of all components.

We will take one metal layer created above the layer below.

The purpose of the IC interconnection is to electrically connect the metal in the layer below to the metal line above. Therefore, the system's product would be Current.

The challenges are as follows:

We need a dielectric material (ILD) to be able to keep the metal line mechanically and separated electrically

ILD - Interlayer dielectric that is typically built of SiO2 or modified SiO2

The metal lines and via are made from Cu

Cu diffuses through the ILD, resulting in shortening - the creation of electrical contacts through ILD

The barrier (typically Ta) is used for preventing Cu diffusion into ILD within the layer

Etch stop layer (typically Si3N4, SiC) aims to prevent Cu diffusion to ILD on the upper layer

Cu is affected by the electromigration effect; therefore, the bottom Barrier that separates the top of the via from the metal at the low layer helps to prevent the formation of huge voids due to Cu electromigration from layer to layer

During the Functional Modeling, we need to take into account the RC-delay that affects the signal and should be as low as possible. RC-delay = R X C where R is the total resistivity of metal layers, and Vias and C is the total capacitance of vertical and horizontal gaps of dielectrics located between metal lines. The resistivity of the metal lines and metal vias should be as low as possible; the Dielectric permittivity of dielectric layers should be as low as possible.

The interconnection part is shown below:

Let's start to create a Functional Model.

The next step is to analyze the manufacturing process of the IC interconnection layer.

Generally, we need to process the structure:

To the structure:

Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.

Let's start, go to the "Model"

We need to complete 13 sequential operations to create a metal layer.

Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.

A typical reasonable process flow is shown below:

After the photolithography operation, the pattern resist is tested with metrological operation (that is not shown in the flow). During the pattern measurements, the critical parameters are measured - Critical Dimensions Measurements (CDM) - size, location, thickness etc. The measurements are invasive therefore, the measurements are performed on the special metrocell and not on the die.

Defect metrology operation is placed after Step 11 - Barrier + Cu-seed deposition - not shown in the flow but will be analyzed in the process flow analysis.

Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"

1 Step is the transformation from the structure:

To the structure:

The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.

The Etch Stop layer deposition is usually performed by the CVD method.

The operation aims to create the Etch Stop layer therefore, the product is the "Etch Stop Layer"

2 Step is the deposition of the ILD layer - a transformation from structure:

To structure:

ILD is typically built of SiO2 or modified SiO2 for the reduction of dielectric permittivity. The Electric permittivity reduction is typically achieved by the creation pores and dipping with C (in the form of methyl), Fluorine

ILD deposition is typically made by the CVD process, where gaseous components are converted into a thin solid film due to the process in plasma.

The operation aims to deposit ILD; therefore, the product (target) of the step is ILD.

3 Step is the deposition of the Sacrificial light-absorbing Layer (SLAL). The main purpose of this layer is to absorb the light during Photolithography and prevent the formation of a standing wave due to the interference of initial reflected light.

The structure:

Should be converted to the structure:

The layer is typically deposited by a spin-on procedure similar to the deposition of a photoresist.

The operation aims to deposit SLAL; therefore, the product (target) of the operation is SLAL.

4th Step is the wafer patterning using Photolithography (PL). PL is a preparation for the next step, which is Dry Etch (Plasma Etch). The purpose of the operation is to deposit the Photo Resist (PR) and create a pattern: the areas that are covered with the PR will not be affected by the Plasma etch, and opened areas will be etched by plasma.

Incoming structure:

Outcoming structure after the PL process should be as follows:

This step creates the pattern for Via etch only. The PL process generally consists of three sequential parts: deposition of the Photo Resist (PR), Exposure - optical exposing of the PR through the special mask, and Development - chemical removal of the exposed part of the PR; unexposed parts will remain on the wafer. (In the case of "negative resist, "the effect is the opposite - exposed parts will remain, while unexposed parts will be removed at the development).

The operation aims to create a patterned photoresist; therefore, its product (target) is Via Patterned PR.

Critical Dimensions Measurements (CDM) are performed after Photolithography. The main parameters of the photoresist pattern are measured and collected to decide whether to continue the wafer's process or return to the rework. The measurements are invasive, so they cannot be done on the die; they are performed on the scribe line between the dies on the specially created metro cell. Every single measurement is performed on the new metro cell because the measurements destroy the metro cell. The fragment of the typical pattern is shown below.

The main purpose of the CDM operation is the information, Product is Information.

5th Step is to etch a Via according to the pattern that was made at the previous step - Via Photo Lithography. The etch is performed with plasma on the all surface of the wafer. The open parts will be etched, while the parts that are covered with the Photoresist (PR) will remain unchanged. The wafer is placed on the chuck, kept with static electricity and treated with plasma containing the ions and/or radicals to be able to convert the ILD in to the gas. Typically, the plasma contains fluorine that converts silicon oxide to gaseous silicon tetrafluoride.

Incoming structure:

Outcoming structure:

This step is a productive operation that provides irreversible changes and increases the value of the product.

The operation aims to create a Via within the ILD according to the patterned resist on the wafer. A via is created due to the conversion of SiO2 of ILD into gaseous SiF4, therefore, its product (target) is a SiF4 - gas.

Wet cleaning is typically performed after the Dry etch process to remove the residual photoresist and sacrificial light-absorbing material and to clean the via from the by-products formed during the Dry etch process—the interaction of plasma with pattern and ILD.

The incoming structure is shown below:

The outcoming structure should look as follows:

The purpose of the operation is to remove the temporary pattern. So, the product (target) of the operation Residue.

The seventh step is depositing the Sacrificial light-absorbing Layer (SLAL). This layer has two purposes: to fill in the via and avoid unnecessary etching within it, to absorb light during photolithography, and to prevent the formation of a standing wave due to the interference of initial reflected light.

The initial structure:

Should be converted to the structure:

The layer is typically deposited by a spin-on procedure similar to the deposition of a photoresist.

The operation aims to deposit SLAL; therefore, the product (target) of the operation is SLAL.

The eighth 8 step is wafer patterning using Photolithography (PL). PL prepares the wafer for the next step, Dry Etch (Plasma Etch). The operation deposits the Photo Resist (PR) and creates a pattern: areas covered with PR are not affected by the Plasma etch, and opened areas are etched by plasma. This operation is for Trench patterning.

Incoming structure:

Outcoming structure after the PL process should be as follows:

This step creates the pattern for Trench etch only. The PL process generally consists of three sequential parts: deposition of the Photo Resist (PR), Exposure - optical exposing of the PR through the special mask, and Development - chemical removal of the exposed part of the PR; unexposed parts will remain on the wafer. (In the case of "negative resist, "the effect is the opposite - exposed parts will remain, while unexposed parts will be removed at the development).

The operation aims to create a patterned photoresist, so its product (target) is Trench-Patterned PR.

Critical Dimensions Measurements (CDM) are performed after Photolithography. The main parameters of the photoresist pattern are measured and collected to decide whether to continue the wafer's process or return to the rework. Because the measurements are invasive, they cannot be performed on the die; they are performed on the scribe line between the dies on the specially created metro cell. Every single measurement is performed on the new metro cell because they destroy the metro cell. The fragment of the typical pattern is shown below.

The structure that is submitted to CDM:

The main purpose of the CDM operation is the information, Product is Information.

9th Step is to etch a Trench for metal wires according to the pattern made at the previous step - Trench Photo Lithography. The etch is performed with plasma on the complete surface of the wafer. The open parts will be etched, while the parts covered with the Photoresist (PR) will remain unchanged. The wafer is placed on the chuck, kept with static electricity and treated with plasma containing the ions and/or radicals to be able to convert the ILD in to the gas. Typically, the plasma contains fluorine that converts silicon oxide to gaseous silicon tetrafluoride.

Incoming structure:

Outcoming structure:

This step is a productive operation that provides irreversible changes and increases the value of the product.

The operation aims to create a Via within the ILD according to the patterned resist on the wafer. A via is created due to the conversion of SiO2 of ILD into gaseous SiF4; therefore, its product (target) is a SiF4 - gas.

Wet cleaning is typically performed after the Dry etch process to remove the residual photoresist and sacrificial light-absorbing material and to clean the via from the by-products formed during the Dry etch process—the interaction of plasma with pattern and ILD.

The incoming structure is shown below:

The outcoming structure should look as follows:

The purpose of the operation is to remove the temporary pattern. So, the product (target) of the operation Residue.

Step 11 is dedicated to depositing a thin layer of Tantalum (Ta) metal. Ta layer aims to prevent diffusion of copper (Cu) in the ILD, which is a silico-oxide-based dielectric material. Ta layer is a barrier between ILD and Cu. The operation's next step is disposing of a thin layer of Cu. This thin Cu layer aims to enable an electrical contact at the next operation - that is, electroplating - bulk Cu deposition by electrolysis. This thin Cu layer is named the Cu-seed layer because it allows the connection of the wafer to the Cathode and the electroplating process. Both Ta-barrier and Cu-seed layers are deposited using the PVD process - Physical Vapour Deposition. The plasma ions and radicles attract the target, which is made of relevant material - either Ta or Cu. The liberated metal aglomerates are deposited on the wafer surface, including the structure walls - vias and trenches of the metal lines.

The incoming structure is shown below:

The outcoming structure is shown below - Ta-barrier and Cu-seed layers are shown as a single black line:

The purpose of the operation is to deposit a Ta-barrier and Cu-seed layer. The Cu-seed layer is deposited on the top of the Ta-barrier layer; therefore, we can assign the Cu-seed layer as a product (target) of the operation.

Defect detection and measurements are typically performed after the Ta-barrier and Cu-seed layer deposition. There are several reasons for the defect metrology after this operation. First, the wafer is in a safe condition - the wafer is covered with a thin layer of Cu that prevents the wafer materials from oxidation by outside air. Second, the conductive thin layer ensures the defects' visibility and prevents the wafer surface's charging. The defects metrology is added to the process to ensure that the operations are completed as per requirements, the equipment operates correctly, and wafers can be released to the next operation.

The fragment of the typical pattern is shown below.

The structure that is submitted to defect metrology operation:

The main purpose of the defect metrology operation is information, and the product is information.

Step 12 - Cu electroplating is the operation that aims to fill in the bulk copper (Cu). The wafer is processed using electroplating equipment. The wafer is connected to the cathode (-) and placed in the electrolyte containing dissolved Cu- sulfate, CuSO4 and sulfuric acid. The anode is made of pure copper, Cu. During the process, the wafer rotates to enhance the diffusion process while the delivery of Cu-ions to the surface of the wafer. The process is performed as regular electroplating: Cu is dissolved on the anode (+) by losing electrons and forming Cu(2+) ions. Cu(2+) ions are reduced on the cathode by accepting electrons to Cu atoms that are deposited in the form of a Cu-metal layer on the surface of the wafer.

The main challenge is the formation of voids within the deposited Cu layer. The reasons for the void formation are as follows:

1. Bubble formation: H(+) discharge and formation of H2 bubbles. This typically occurs when the voltage is too high, which results from improper electrical contact, the Cu-seed layer not being thick enough, etc.
2. Bubbles remaining: Air should be completely replaced by the electrolyte, but if air bubbles remain encapsulated by the electrolyte and Cu deposit
3. Electrolyte drops: the electrolyte should be completely replaced by the Cu that is electroplated during the process, but the growing Cu deposit can encapsulate some drops of the electrolyte.

The deposition is always above the required level to ensure that the bubbles and some defects are mainly concentrated in the top part of the deposit and will be removed at the next operation.

The incoming structure is shown below:

The outcoming structure is shown here:

The purpose of the operation is to plate the Cu, so the product is Electroplated Cu

Step 13 - Excessive Cu and Ta-barrier removal by polish aims to remove all metal parts that make contact between different metal lines that should not be connected. The operation is performed using the chemical-mechanical polishing (CMP) method.

The wafer is kept in the holder and pushed face down to the pad. A slurry containing fumed silica or other relevant material is poured on the pad to ensure the material is removed by polishing. A special conditioner cleans the pad from the residual material created during the polishing. The very general scheme of the polisher is shown below (taken from the Wikipedia):

The incoming structure is shown below:

The outcoming structure is shown here:

The purpose of the operation is to remove the excessive material - Cu, Ta, ILD. The operation's product is excessive material.

The next step is to analyze the manufacturing process of the IC interconnection layer.

Generally, we need to process the structure:

To the structure:

Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.

Let's start, go to the "Model"

We need to complete 13 sequential operations to create a metal layer.

Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.

A typical reasonable process flow is shown below:

After the photolithography operation, the pattern resist is tested with metrological operation (that is not shown in the flow). During the pattern measurements, the critical parameters are measured - Critical Dimensions Measurements (CDM) - size, location, thickness etc. The measurements are invasive therefore, the measurements are performed on the special metrocell and not on the die.

Defect metrology operation is placed after Step 11 - Barrier + Cu-seed deposition - not shown in the flow but will be analyzed in the process flow analysis.

Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"

1 Step is the transformation from the structure:

To the structure:

The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.

The Etch Stop layer deposition is usually performed by the CVD method.

The operation aims to create the Etch Stop layer therefore, the product is the "Etch Stop Layer"

2 Step is the deposition of the ILD layer - a transformation from structure:

To structure:

ILD is typically built of SiO2 or modified SiO2 for the reduction of dielectric permittivity. The Electric permittivity reduction is typically achieved by the creation pores and dipping with C (in the form of methyl), Fluorine

ILD deposition is typically made by the CVD process, where gaseous components are converted into a thin solid film due to the process in plasma.

The operation aims to deposit ILD; therefore, the product (target) of the step is ILD.

3 Step is the deposition of the Sacrificial light-absorbing Layer (SLAL). The main purpose of this layer is to absorb the light during Photolithography and prevent the formation of a standing wave due to the interference of initial reflected light.

The structure:

Should be converted to the structure:

The layer is typically deposited by a spin-on procedure similar to the deposition of a photoresist.

The operation aims to deposit SLAL; therefore, the product (target) of the operation is SLAL.

4th Step is the wafer patterning using Photolithography (PL). PL is a preparation for the next step, which is Dry Etch (Plasma Etch). The purpose of the operation is to deposit the Photo Resist (PR) and create a pattern: the areas that are covered with the PR will not be affected by the Plasma etch, and opened areas will be etched by plasma.

Incoming structure:

Outcoming structure after the PL process should be as follows:

This step creates the pattern for Via etch only. The PL process generally consists of three sequential parts: deposition of the Photo Resist (PR), Exposure - optical exposing of the PR through the special mask, and Development - chemical removal of the exposed part of the PR; unexposed parts will remain on the wafer. (In the case of "negative resist, "the effect is the opposite - exposed parts will remain, while unexposed parts will be removed at the development).

The operation aims to create a patterned photoresist; therefore, its product (target) is Via Patterned PR.

Critical Dimensions Measurements (CDM) are performed after Photolithography. The main parameters of the photoresist pattern are measured and collected to decide whether to continue the wafer's process or return to the rework. The measurements are invasive, so they cannot be done on the die; they are performed on the scribe line between the dies on the specially created metro cell. Every single measurement is performed on the new metro cell because the measurements destroy the metro cell. The fragment of the typical pattern is shown below.

The main purpose of the CDM operation is the information, Product is Information.

5th Step is to etch a Via according to the pattern that was made at the previous step - Via Photo Lithography. The etch is performed with plasma on the all surface of the wafer. The open parts will be etched, while the parts that are covered with the Photoresist (PR) will remain unchanged. The wafer is placed on the chuck, kept with static electricity and treated with plasma containing the ions and/or radicals to be able to convert the ILD in to the gas. Typically, the plasma contains fluorine that converts silicon oxide to gaseous silicon tetrafluoride.

Incoming structure:

Outcoming structure:

This step is a productive operation that provides irreversible changes and increases the value of the product.

The operation aims to create a Via within the ILD according to the patterned resist on the wafer. A via is created due to the conversion of SiO2 of ILD into gaseous SiF4, therefore, its product (target) is a SiF4 - gas.

Wet cleaning is typically performed after the Dry etch process to remove the residual photoresist and sacrificial light-absorbing material and to clean the via from the by-products formed during the Dry etch process—the interaction of plasma with pattern and ILD.

The incoming structure is shown below:

The outcoming structure should look as follows:

The purpose of the operation is to remove the temporary pattern. So, the product (target) of the operation Residue.