login
Updated 10/22/2024
0

Optimizing IC Interconnection: A Functional Approach to Innovation (Stay updated on the project's progress)

Functional Modeling of the created layer #

We need to create a Functional Model of IC Interconnection to understand and learn the functional and problem ranks of all components.

We will take one metal layer created above the layer below.

The purpose of the IC interconnection is to electrically connect the metal in the layer below to the metal line above. Therefore, the system's product would be Current.

The challenges are as follows:

We need a dielectric material (ILD) to be able to keep the metal line mechanically and separated electrically

ILD - Interlayer dielectric that is typically built of SiO2 or modified SiO2

The metal lines and via are made from Cu

Cu diffuses through the ILD, resulting in shortening - the creation of electrical contacts through ILD

The barrier (typically Ta) is used for preventing Cu diffusion into ILD within the layer

Etch stop layer (typically Si3N4, SiC) aims to prevent Cu diffusion to ILD on the upper layer

Cu is affected by the electromigration effect; therefore, the bottom Barrier that separates the top of the via from the metal at the low layer, helps to prevent the formation of huge voids due to Cu electromigration from layer to layer

The interconnection part is shown below:

Let's start to create a Functional Model.


Operational Effectiveness – OE

Effective

Ineffective

OE 2.17
Operational Perfectness - OP

Basic functions

Components

Supersystems

OP 0.1
Functional rank
Problematic rank
Barrier - top layer
10
10
Cu metal - top layer
8.6
1.7
Metal - bottom layer
8.6
Cu via - top layer
5.7
1.3
ILD - top layer
4.3
ILD - bottom layer
2.9
Etch stop layer
2.9
Barrier - bottom layer
2.9
0.8
Cu - diffusion
1.1
Cu electromigration voids
6.3

Exciting result - the most functional component for current providing is not a metal line but a component that keeps the metal line:

  • If we assign that "Barrier Keeps Metal Line" (see the basic version) - the most functional component becomes Barrier
  • If we assign that "ILD Keeps Metal Line" (next version) - the most functional component becomes ILD

The conclusion - the carrier has higher functionality than the metal line that provides electrical current.


So, we need to think about how to eliminate barriers and delegate its functions to another component - small air gaps between Cu metal lines and ILD seem to be very perspective from the standpoint of both Cu diffusion prevention and RC-delay reduction

The possible configuration can be as shown below:

The Functional Model is in the Proposed Version


The Air Gaps model seems much better and also helps to prevent void formation due to Cu electromigration - the void already exists. It might happen that due to very strong Cu-electromigration, the shape of the via and metal line will be slightly affected, but no voids will be created within the metal line or within the metal via.

Oct 13 2024 11:05:29 am
Version: Basic version, Component: Barrier - top layer #
Contradiction:
If
Barrier - top layer remains unchanged
Then
Barrier - top layer Keeps Cu metal - top layer
But
Barrier - top layer Reduces Cu metal - top layer
Improving parameter
Description of what is improving:
No diffusion of Cu or voids formation due to electromigration effect - Metal line remains unchanged
Selected improving parameter:
Shape
Worsening parameter
Description of what is worsening:
The barrier takes the volume of the via and trench therefore, the volume of the metal via and metal line becomes smaller, reducing the conductivity of the line and affecting the current as a product
Selected worsening parameter:
Loss of substance
Matching principles:
  • 3
    Local quality
  • 5
    Merging
  • 29
    Pneumatics or hydraulics
  • 35
    Parameter changes
  • Oct 18 2024 8:49:34 am
    Process Functional Modeling #

    The next step is to analyze the manufacturing process of the IC interconnection layer.

    Generally, we need to process the structure:

    To the structure:


    Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.

    Let's start, go to the "Model"


    We need to complete 13 sequential operations to create a metal layer.

    Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.


    A typical reasonable process flow is shown below:

    Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"

    Step 1 Etch Stop Deposition

    3
    1.98
    OE 1.51

    Step 2 ILD Deposition

    Step 3 Sacrificial Layer Deposition for Via

    Step 4 Photolithography patterning for Via

    Step 5 Via Etch

    Step 6 Wet Cleaning after Via Etch

    Step 7 Sacrificial Layer Deposition for Trench

    Step 8 Photolithography Patterning for Trench

    Step 9 Trench Etch for Metal Line

    Step 10 Wet Cleaning after Trench Etch

    Step 11 Ta-Barrier + Cu-Seed layers Deposition

    Step 12 Cu Electroplating

    Step 13 Excessive Cu and Barrier Removal by Polish

    Productive operations effectiveness

    Effective

    Ineffective

    Operation types breakdown

    Productive

    Providing

    Corrective

    Metrology

    Operation TypeDoes it increase cost?Does it increase product value?Recommendation
    Productive
    YesYesImprove
    Providing
    YesNoEliminate
    Corrective
    YesNoEliminate
    Metrology
    YesNoEliminate
    OperationTypeMeritRecommendation
    Step 1 Etch Stop Deposition
    Productive
    OE 1.51
    Consider improving
    Oct 19 2024 1:03:56 pm
    Step 1 Etch Stop Deposition #
    (by Process Functional Modeling)

    1 Step is the transformation from the structure:

    To the structure:


    The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.

    The Etch Stop layer deposition is usually performed by the CVD method.

    The operation aims to create the Etch Stop layer therefore the product is the "Etch Stop Layer"

    Operational Effectiveness – OE

    Effective

    Ineffective

    OE 1.51
    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    OP 0.18
    Functional rank
    Problematic rank
    Plasma
    10
    CVD system
    5.5
    Initial layer
    4
    Gaseous Chemicals
    3.5
    Wafer
    3
    Cu - Initial layer
    2.5
    ILD - Initial layer
    2.5
    Chuck
    2
    Vacuum pump
    10
    By-product gases
    2.6
    Air
    9.2

    It is exciting results:

    Plasma is the most functional component - we have to think about plasma for effective improvement of the process

    Vacuum pump came out as the most problematic component of the system - we have to think about how to eliminate or replace the vacuum pump - Interesting

    Oct 20 2024 10:53:40 am
    Step 2 ILD Deposition #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:54:15 am
    Step 3 Sacrificial Layer Deposition for Via #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:55:01 am
    Step 4 Photolithography patterning for Via #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:56:01 am
    Step 5 Via Etch #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:57:00 am
    Step 6 Wet Cleaning after Via Etch #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:57:48 am
    Step 7 Sacrificial Layer Deposition for Trench #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 10:59:06 am
    Step 8 Photolithography Patterning for Trench #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:01:21 am
    Step 9 Trench Etch for Metal Line #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:02:08 am
    Step 10 Wet Cleaning after Trench Etch #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:03:35 am
    Step 11 Ta-Barrier + Cu-Seed layers Deposition #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:04:21 am
    Step 12 Cu Electroplating #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:05:30 am
    Step 13 Excessive Cu and Barrier Removal by Polish #
    (by Process Functional Modeling)
    Operational Effectiveness – OE

    Effective

    Ineffective

    Operational Perfectness - OP

    Basic functions

    Components

    Supersystems

    Functional rank
    Problematic rank
    Component
    No impact
    Oct 20 2024 11:06:26 am
    Login to comment

    Similar projects

    The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)

    Anatoly Agulyansky avatar
    Anatoly Agulyansky
    Anatoly Agulyansky avatar
    Mike Agulyansky avatar
    Alex Agulyansky avatar

    Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.

    Anatoly Agulyansky avatar
    Anatoly Agulyansky

    The project was dedicated to production yield improvement in microchip manufacturing. The bumps are created on the top of a wafer and used for the final test of all dies. Only good dies are taken for the packaging. All dies that fail the test will be scrapped. The process yield depends on the amount of "good" and "bad" dies. It was revealed that in some cases, the time between the end of the process and the final test impacts the yield. The longer the dwelling, the more dies fail the final test. If the dwelling exceeds hundreds of hours, the amount of failed dies becomes dramatically high, which results in the scrapping of the whole wafer. The problem was analyzed and solved.

    Anatoly Agulyansky avatar
    Anatoly Agulyansky
    Richard Platt avatar
    Alex Agulyansky avatar