We need to create a Functional Model of IC Interconnection to understand and learn the functional and problem ranks of all components.
We will take one metal layer created above the layer below.
The purpose of the IC interconnection is to electrically connect the metal in the layer below to the metal line above. Therefore, the system's product would be Current.
The challenges are as follows:
We need a dielectric material (ILD) to be able to keep the metal line mechanically and separated electrically
ILD - Interlayer dielectric that is typically built of SiO2 or modified SiO2
The metal lines and via are made from Cu
Cu diffuses through the ILD, resulting in shortening - the creation of electrical contacts through ILD
The barrier (typically Ta) is used for preventing Cu diffusion into ILD within the layer
Etch stop layer (typically Si3N4, SiC) aims to prevent Cu diffusion to ILD on the upper layer
Cu is affected by the electromigration effect; therefore, the bottom Barrier that separates the top of the via from the metal at the low layer helps to prevent the formation of huge voids due to Cu electromigration from layer to layer
During the Functional Modeling, we need to take into account the RC-delay that affects the signal and should be as low as possible. RC-delay = R X C where R is the total resistivity of metal layers, and Vias and C is the total capacitance of vertical and horizontal gaps of dielectrics located between metal lines. The resistivity of the metal lines and metal vias should be as low as possible; the Dielectric permittivity of dielectric layers should be as low as possible.
The interconnection part is shown below:
Let's start to create a Functional Model.
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Exciting result - the most functional component for current providing is not a metal line but a component that keeps the metal line:
The conclusion - the carrier has higher functionality than the metal line that provides electrical current.
So, we need to think about how to eliminate barriers and delegate its functions to another component - small air gaps between Cu metal lines and ILD seem to be very perspective from the standpoint of both Cu diffusion prevention and RC-delay reduction
The possible configuration can be as shown below:
The Functional Model is in the Proposed Version
The Air Gaps model seems much better and also helps to prevent void formation due to Cu electromigration - the void already exists. It might happen that due to very strong Cu-electromigration, the shape of the via and metal line will be slightly affected, but no voids will be created within the metal line or within the metal via.
If | Barrier - top layer remains unchanged |
---|---|
Then | Barrier - top layer Keeps Cu metal - top layer |
But | Barrier - top layer Reduces Cu metal - top layer |
The next step is to analyze the manufacturing process of the IC interconnection layer.
Generally, we need to process the structure:
To the structure:
Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.
Let's start, go to the "Model"
We need to complete 13 sequential operations to create a metal layer.
Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.
A typical reasonable process flow is shown below:
Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"
Step 1 Etch Stop Deposition
Step 2 ILD Deposition
Step 3 Sacrificial Layer Deposition for Via
Step 4 Photolithography patterning for Via
Step 5 Via Etch
Step 6 Wet Cleaning after Via Etch
Step 7 Sacrificial Layer Deposition for Trench
Step 8 Photolithography Patterning for Trench
Step 9 Trench Etch for Metal Line
Step 10 Wet Cleaning after Trench Etch
Step 11 Ta-Barrier + Cu-Seed layers Deposition
Step 12 Cu Electroplating
Step 13 Excessive Cu and Barrier Removal by Polish
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Operation Type | Does it increase cost? | Does it increase product value? | Recommendation |
---|---|---|---|
Productive | Yes | Yes | Improve |
Providing | Yes | No | Eliminate |
Corrective | Yes | No | Eliminate |
Metrology | Yes | No | Eliminate |
Operation | Type | Merit | Recommendation |
---|---|---|---|
Step 1 Etch Stop Deposition | Productive | OE 1.51 | Consider improving |
Step 2 ILD Deposition | Productive | OE 2.57 | Consider improving |
Step 3 Sacrificial Layer Deposition for Via | Providing | OE 1.35 | Consider eliminating |
Step 4 Photolithography patterning for Via | Providing | OE 4.01 | Consider eliminating |
1 Step is the transformation from the structure:
To the structure:
The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.
The Etch Stop layer deposition is usually performed by the CVD method.
The operation aims to create the Etch Stop layer therefore, the product is the "Etch Stop Layer"
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It is exciting results:
Plasma is the most functional component - we have to think about plasma for effective improvement of the process
Vacuum pump came out as the most problematic component of the system - we have to think about how to eliminate or replace the vacuum pump - Interesting
2 Step is the deposition of the ILD layer - a transformation from structure:
To structure:
ILD is typically built of SiO2 or modified SiO2 for the reduction of dielectric permittivity. The Electric permittivity reduction is typically achieved by the creation pores and dipping with C (in the form of methyl), Fluorine
ILD deposition is typically made by the CVD process, where gaseous components are converted into a thin solid film due to the process in plasma.
The operation aims to deposit ILD; therefore, the product (target) of the step is ILD.
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Stupid question. Why do we need a vacuum for ILD deposition? I see only one possible reason - to create a free pathway that is long enough for plasma creation. OK. We need to think about how to ensure plasma and avoid deep vacuum. ILD that is SiO2 or modifications of SiO2 do not need a vacuum. More than that, the lack of oxygen
3 Step is the deposition of the Sacrificial light-absorbing Layer (SLAL). The main purpose of this layer is to absorb the light during Photolithography and prevent the formation of a standing wave due to the interference of initial reflected light.
The structure:
Should be converted to the structure:
The layer is typically deposited by a spin-on procedure similar to the deposition of a photoresist.
The operation aims to deposit SLAL; therefore, the product (target) of the operation is SLAL.
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There are too many components. It would be easier and more effective to use hot air to solidify the Sacrificial Light Absorbing Material when it is on the wafer. So, the process seems to be like this: Wafer is kept in the chuck and rotated. The liquid stuff is poured on the rated wafer, and hot air solidifies the material on the wafer. The local flow of the air will preserve the wafer from the contamination of the layer. A chamber filter and Fan will not be needed.
4th Step is the wafer patterning using Photolithography (PL). PL is a preparation for the next step, which is Dry Etch (Plasma Etch). The purpose of the operation is to deposit the Photo Resist (PR) and create a pattern: the areas that are covered with the PR will not be affected by the Plasma etch, and opened areas will be etched by plasma.
Incoming structure:
Outcoming structure after the PL process should be as follows:
This step creates the pattern for Via etch only. The PL process generally consists of three sequential parts: deposition of the Photo Resist (PR), Exposure - optical exposing of the PR through the special mask, and Development - chemical removal of the exposed part of the PR; unexposed parts will remain on the wafer. (In the case of "negative resist, "the effect is the opposite - exposed parts will remain, while unexposed parts will be removed at the development).
The operation aims to create a patterned photoresist; therefore, its product (target) is Via Patterned PR.
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Photolithography does not add value to the product. The PL operation is very complex, so there is no reason to develop the operation and equipment. The PL operation is very expensive and must be simplified and eliminated.
The Exposed Resist is the most functional component. So, let's document some ideas for simplification of the PL process: