We need to create a Functional Model of IC Interconnection to understand and learn the functional and problem ranks of all components.
We will take one metal layer created above the layer below.
The purpose of the IC interconnection is to electrically connect the metal in the layer below to the metal line above. Therefore, the system's product would be Current.
The challenges are as follows:
We need a dielectric material (ILD) to be able to keep the metal line mechanically and separated electrically
ILD - Interlayer dielectric that is typically built of SiO2 or modified SiO2
The metal lines and via are made from Cu
Cu diffuses through the ILD, resulting in shortening - the creation of electrical contacts through ILD
The barrier (typically Ta) is used for preventing Cu diffusion into ILD within the layer
Etch stop layer (typically Si3N4, SiC) aims to prevent Cu diffusion to ILD on the upper layer
Cu is affected by the electromigration effect; therefore, the bottom Barrier that separates the top of the via from the metal at the low layer, helps to prevent the formation of huge voids due to Cu electromigration from layer to layer
The interconnection part is shown below:
Let's start to create a Functional Model.
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Exciting result - the most functional component for current providing is not a metal line but a component that keeps the metal line:
The conclusion - the carrier has higher functionality than the metal line that provides electrical current.
So, we need to think about how to eliminate barriers and delegate its functions to another component - small air gaps between Cu metal lines and ILD seem to be very perspective from the standpoint of both Cu diffusion prevention and RC-delay reduction
The possible configuration can be as shown below:
The Functional Model is in the Proposed Version
The Air Gaps model seems much better and also helps to prevent void formation due to Cu electromigration - the void already exists. It might happen that due to very strong Cu-electromigration, the shape of the via and metal line will be slightly affected, but no voids will be created within the metal line or within the metal via.
If | Barrier - top layer remains unchanged |
---|---|
Then | Barrier - top layer Keeps Cu metal - top layer |
But | Barrier - top layer Reduces Cu metal - top layer |
The next step is to analyze the manufacturing process of the IC interconnection layer.
Generally, we need to process the structure:
To the structure:
Let's analyze all the steps needed to make an additional interconnection layer. We will use very general operations of the typical process used in many fabs for manufacturing BEOL layers.
Let's start, go to the "Model"
We need to complete 13 sequential operations to create a metal layer.
Generally speaking, two types of operations in semiconductor manufacturing aim to either deposit something or remove something.
A typical reasonable process flow is shown below:
Let's analyze the process using Process Functional Modeling, a creative thinking tool. No metrology operations were taken into account. Go to "Model"
Step 1 Etch Stop Deposition
Step 2 ILD Deposition
Step 3 Sacrificial Layer Deposition for Via
Step 4 Photolithography patterning for Via
Step 5 Via Etch
Step 6 Wet Cleaning after Via Etch
Step 7 Sacrificial Layer Deposition for Trench
Step 8 Photolithography Patterning for Trench
Step 9 Trench Etch for Metal Line
Step 10 Wet Cleaning after Trench Etch
Step 11 Ta-Barrier + Cu-Seed layers Deposition
Step 12 Cu Electroplating
Step 13 Excessive Cu and Barrier Removal by Polish
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Operation Type | Does it increase cost? | Does it increase product value? | Recommendation |
---|---|---|---|
Productive | Yes | Yes | Improve |
Providing | Yes | No | Eliminate |
Corrective | Yes | No | Eliminate |
Metrology | Yes | No | Eliminate |
Operation | Type | Merit | Recommendation |
---|---|---|---|
Step 1 Etch Stop Deposition | Productive | OE 1.51 | Consider improving |
1 Step is the transformation from the structure:
To the structure:
The Etch Stop layer is mainly needed to preserve the Cu diffusion to the ILD of the top layer - the top barrier. It is typically made of Si3N4 or SiC because increased density is needed to ensure barrier properties against Cu diffusion.
The Etch Stop layer deposition is usually performed by the CVD method.
The operation aims to create the Etch Stop layer therefore the product is the "Etch Stop Layer"
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It is exciting results:
Plasma is the most functional component - we have to think about plasma for effective improvement of the process
Vacuum pump came out as the most problematic component of the system - we have to think about how to eliminate or replace the vacuum pump - Interesting
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The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
The project was dedicated to production yield improvement in microchip manufacturing. The bumps are created on the top of a wafer and used for the final test of all dies. Only good dies are taken for the packaging. All dies that fail the test will be scrapped. The process yield depends on the amount of "good" and "bad" dies. It was revealed that in some cases, the time between the end of the process and the final test impacts the yield. The longer the dwelling, the more dies fail the final test. If the dwelling exceeds hundreds of hours, the amount of failed dies becomes dramatically high, which results in the scrapping of the whole wafer. The problem was analyzed and solved.