Intro - why to use Cu electroplating
Copper electroplating is one of the most elegant processes in semiconductor manufacturing. It is simple in principle, relatively low cost, and capable of filling extremely complex structures. Fine vias, long trenches, high-aspect-ratio features — all can be filled simultaneously in a single operation. That is why copper electrodeposition became the backbone of BEOL metallization.
The structure after Cu-Electroplating. The structure after Polish - CMP.
Equipment and the process
Inside a typical electroplating tool, the wafer is placed horizontally into the electrolyte at the top of an electrolyte bath. At the bottom of the cell sits the copper anode. The bath contains an aqueous solution of CuSO₄ and H₂SO₄, diluted in DI water, together with carefully engineered organic additives that control leveling, suppression, acceleration, and surface tension.
The wafer enters the bath from above. It rotates during plating to improve hydrodynamics and mass transport. Electrical contact is made at the wafer bevel. The front side remains fully exposed to the electrolyte.
Before plating can occur, the wafer must be conductive. Therefore, a thin copper seed layer is deposited over the Ta/TaN diffusion barrier. This Cu-seed layer distributes electrical potential across the wafer surface and enables electrolysis everywhere.
When DC voltage is applied, copper dissolves from the anode (+) and deposits onto the wafer surface - cathode (-). According to Faraday’s law, the deposited thickness is proportional to the local current density. In theory, if the potential is uniform, the thickness should also be uniform.
A schematic Cu-electroplating process is shown below - (Ref. https://www.mks.com/n/metal-thin-films )
Challenge and explanation
But the reality is different. The seed layer is thin. It has finite sheet resistance. Although the voltage is applied to the entire wafer, the current must travel laterally through this thin copper film. Near the wafer edge, where electrical contact is made, the resistance path is short. Current density is high. Deposition is fast. The copper layer becomes thick.
As the distance from the contact increases, the lateral resistance increases. The effective cathodic potential decreases slightly due to IR drop. Current density decreases. Deposition slows down. In the center of the wafer, copper becomes noticeably thinner.
The system behaves exactly as physics predicts — but not as manufacturing desires.
The consequence is radial non-uniformity: thick at the edge, thin at the center.
Currently applied resolutions
To compensate for this effect, the industry deposits more copper than necessary. The wafer is intentionally overplated. Afterwards, Chemical Mechanical Polishing (CMP) removes the excess metal. This strategy restores planarity and thickness control, but it increases plating time, copper consumption, slurry usage, equipment wear, and overall cost. We deposit what we do not need, and then we remove it.
Another known solution is the use of a dummy cathode, also called a current thief. A conductive ring is placed around the wafer periphery. It attracts part of the current and reduces edge deposition. The uniformity improves, but copper is now deposited onto a surface that has no product value. Again, material and energy are consumed without creating value.
Thus, the system reveals a contradiction.
The target of the project
We need a thin seed layer to reduce cost and improve integration. But thin means resistive. Resistive means non-uniform current. Non-uniform current means non-uniform deposition. Non-uniform deposition means overplating and CMP waste.
The electroplating process is not failing. It obeys physics. The question is whether we can redesign the system so that physics works for us, not against us.
This is the starting point of the project: to analyze the copper electroplating system functionally, understand where uniformity is lost, and develop an innovative method that improves radial thickness control without increasing cost, complexity, or material waste.
Now the system is clearly defined. The contradiction is visible. The opportunity for innovation is real.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project investigates radial non-uniformity of CDO low-k dielectric deposited by PECVD and its possible impact on wafer performance. Final test data indicate that faster dies are mainly located closer to the wafer center, while slower dies are more often found near the wafer periphery. The corresponding RC-delay trend also increases toward the wafer edge. The focus of the project is the capacitance component of RC-delay. CDO is expected to provide a low dielectric constant between BEOL metal lines, but the deposited film may not have uniform properties across the wafer. Near the wafer edge, the process can be influenced by different gas flow, plasma behavior, residence time, temperature, and pumping conditions. This may lead to stronger oxidation and deeper precursor decomposition near the periphery, forming CDO that is more oxygen-rich, less carbon-rich, denser, and closer in behavior to SiO₂. As a result, the dielectric constant k may increase toward the wafer edge, causing higher interline capacitance, higher RC-delay, and lower die speed. The project uses Functional Modeling to understand how PECVD chamber components and process conditions affect CDO film properties. The goal is to identify the main functional and problematic interactions and propose directions for compensation, such as radial gas-flow tuning, multi-zone showerhead design, edge compensation flow, and local plasma or temperature control.