Non-uniform deposition of Cu on the wafer during Cu-electroplating at the BEOL of semiconductor manufacturing
Optimize the seed layer deposition process to incorporate radial thickness grading, with slightly thicker Cu in the center via targeted PVD parameters, balancing overall thinness while countering the inherent current distribution bias during electroplating.
Cu layer is thicker on the periphery of the wafer and systematically thinner while moving from the periphery to the mid and central part of the wafer
Incorporate radial electrolyte flow channels in the plating cell to create targeted convective enhancement at the wafer center, compensating for lower current density and promoting uniform ion supply without altering overall process conditions.
During electroplating, Cu is deposited more on the peripheral area that is near the electrical contact on the bevel and less on the mid and central area of the wafer
Pre-treat the wafer bevel with a localized conductive enhancement layer (e.g., via selective electroless deposition) to lower contact resistance and ensure even current injection across the periphery without altering the overall seed thickness.
Current density is higher at the periphery (near the contact on the bevel) and lower when far from the contact, in the mid and expecially central zone of the wafer
Implement a rotating auxiliary electrode positioned symmetrically around the wafer, electrically isolated but capacitively coupled to dynamically average out peripheral current concentration during plating.
The thin Cu seed layer has high sheet resistance, causing IR voltage drop with increasing distance from the bevel contact
Incorporate a post-seed annealing step in a reducing atmosphere to recrystallize the Cu seed layer, reducing grain boundary scattering and lowering sheet resistance by 20-30% without increasing thickness.
The Cu-electrodeposition process strongly depends on the current density
Incorporate a conductive mesh or auxiliary cathode ring positioned conformally around the wafer periphery, biased to redistribute current evenly and minimize IR drops from the bevel contact without wasting material on non-productive surfaces.
Current density controls the kinetics of Cu deposition reaction at the wafer surface - the deposition is controled on the kinetics part of the deposition process
Formulate the electrolyte with optimized concentrations of kinetic accelerators, such as bis(3-sulfopropyl) disulfide (SPS), to lower the activation energy of the Cu reduction reaction, making deposition less sensitive to local current density variations and shifting control toward mass transport.
Cu electrodeposition reaction is kinetically controlled at standard overpotentials used in process
Implement a pre-plating surface activation rinse using a dilute sulfuric acid or halide-containing solution to chemisorb species on the Cu seed layer, reducing the kinetic barrier for electron transfer and enabling faster reaction rates at existing overpotentials.
Diffusion of Cu(2+) ions occurs faster than the electrical discharge of the ion on the cathode
Increase the electroplating bath temperature by 5-10°C to disproportionately accelerate the temperature-sensitive reaction kinetics relative to diffusion, thereby reducing kinetic limitations.
The process conditions provide too slow an electrical discharge and too fast diffusion
Implement pulsed current electrodeposition with tailored duty cycles and pulse frequencies to intermittently boost discharge kinetics while allowing diffusion to equilibrate, reducing the kinetic limitation under standard conditions
Electrolyte composition and process conditions enhance Cu2+ ion mobility for fast diffusion, but do not accelerate cathodic reaction kinetics adequately
Increase the cathodic overpotential through refined voltage control in the plating recipe to enhance reaction kinetics without exceeding mass transport limits, ensuring uniform deposition across the wafer
Inside a typical electroplating tool, the wafer is placed horizontally into the electrolyte at the top of an electrolyte bath. At the bottom of the cell sits the copper anode. The bath contains an aqueous solution of CuSO₄ and H₂SO₄, diluted in DI water, together with carefully engineered organic additives that control leveling, suppression, acceleration, and surface tension.
The wafer enters the bath from above. It rotates during plating to improve hydrodynamics and mass transport. Electrical contact is made at the wafer bevel. The front side remains fully exposed to the electrolyte.
Before plating can occur, the wafer must be conductive. Therefore, a thin copper seed layer is deposited over the Ta/TaN diffusion barrier. This Cu-seed layer distributes electrical potential across the wafer surface and enables electrolysis everywhere.
When DC voltage is applied, copper dissolves from the anode (+) and deposits onto the wafer surface - cathode (-). According to Faraday’s law, the deposited thickness is proportional to the local current density. In theory, if the potential is uniform, the thickness should also be uniform.
Actually, Cu2+ ions are coming to the entire surface of the wafer, discharging faster on the peripheral parts of the Cu-seed than in the central part of the Cu-seed.
A schematic Cu-electroplating process is shown below - (Ref. https://www.mks.com/n/metal-thin-films )
Effective
Ineffective
Basic functions
Components
Supersystems
Cu(2+) ions | 12 36 |
Electrolyte | 8 8 |
Wafer | 5 |
Cu-plated on
wafer periphery | 5 5 |
Cu-plated on the mid
and central part of the wafer | 5 5 |
Contacts | 4 8 |
Cu-seed on the
mid and center | 3 3 |
Cu-seed on
the perephery | 3 3 |
Additives to
the electrolyte | 2 2 |
H2SO4 | 2 |
What did we learned from the creation of the Functional Model?
The most problematic component is Cu2+ ions that discharge on the cathode, depending on the distance from the contact. This means that the deposition strongly depends on the local voltage.
So, this means the process is strongly managed by the applied voltage. Our goal is to destroy the strong dependence; we need to reduce the sensitivity of the Cu deposition to the voltage.
This is achievable if we move the process from the kinetic mechanism to the diffusion mechanism - we should make the process dependent on the diffusion and not on discharge. We need to increase the rate of discharge and reduce the rate of diffusion of the ions.
Copper electroplating is applied to fill all the structures on the silicon wafer during semiconductor manufacturing. The wafer is first covered with a thin Cu seed layer to enable electrical conductivity, allowing the application of potential across the wafer surface for the electrolysis of copper. Electrical contact is made at the wafer bevel, and the wafer is immersed in the electrolyte of the electroplating bath. The electroplating tool features a copper anode and the electrolyte solution, with the wafer serving as the cathode. The wafer rotates during the process to enhance hydrodynamics, and copper is deposited onto the wafer surface.
The primary challenge is non-uniform deposition of the Cu layer, where the deposit is thicker at the periphery (near the edge) and thinner in the central zone of the wafer. This radial non-uniformity arises due to the thin seed layer's resistance, leading to higher current density and faster deposition near the bevel of the wafer, where the electrical path is shorter. In the mid and central area of the wafer, the IR drop increases, therefore the current density reduces.
To perform CEC analysis, we can break down the chain: Start with the process parameters (thin Cu seed, bevel contact, rotation, electrolyte composition), identify intermediate effects (lateral current flow, IR drop), and trace to the root cause of non-uniformity, aiming to uncover opportunities for improvement without increasing costs or waste.
Non-uniform layer of Cu deposits on sislicon wafer at Cu-electroplating
Enhance mass transport uniformity by integrating a radial flow impeller system that directs electrolyte preferentially toward the wafer center without increasing overall agitation energy.
More Cu deposites on the periphery and less on the central part of the wafer
Adopt pulsed current electroplating mode with tailored on-off cycles and amplitudes to reduce the effective IR drop across the seed layer, promoting more uniform deposition rates radially.
Thin Cu seed layer exhibits high sheet resistance, increasing IR drop towards wafer center
Design the seed layer with a slight radial thickness gradient (thicker toward center via masked PVD) to compensate for IR drop, ensuring average thickness remains thin for cost control.
The wafer is connected to the electricity through the wafer bevel
Incorporate an auxiliary conductive mesh or foil overlay on the wafer bevel during plating to equalize potential across the seed layer without altering the seed thickness.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage