Process: Cu-electroplating in semiconductor manufacturing
Problem: Non-uniform deposition - the thickness of the deposited Cu is high on the periphery of the wafer and decreases while moving to the central area of the wafer.
Current solutions: Deposit a thick layer of Cu and remove with polish (CMP), add a dummy cathode around the wafer to reduce the deposition at the periphery of the wafer.
Creative tools used: Problem statement analysis, 5Whys, Functional Modeling
Root cause found: The root cause is radial IR drop in the thin Cu seed layer, which causes spatial variation of local cathodic overpotential.
Fundamentals: The electrolysis process is described by the curve current vs voltage as shown on the chart:
There are two mechanisms of deposition:
As you can see, the Kinetic process strongly depends on the voltage - even a small variation of the voltage results in a big variation of the current, and results in a big variation of the deposited Cu - thikness.
The diffusion mechanism "keeps" the current stable versus the voltage variation.
The non-uniformity is amplified because the process operates predominantly in the kinetically controlled regime.
Correct Innovation Strategy
The objective is to reduce the sensitivity of deposition rate to local potential variations, rather than simply increasing seed thickness.
The strategic direction is:
Move the operating point closer to the diffusion-limited regime, where:
Current density ≈ limiting current
and becomes less sensitive to small voltage variations.
Proposed solutions:
To increase the rate of discharge of Cu-ions and reduce the diffusion of Cu-ions in the electrolyte.
Clean Final Strategic Statement:
The project does not aim to increase seed thickness or compensate for waste deposition. Instead, it aims to redesign operating conditions so that copper deposition becomes less sensitive to local voltage variations caused by seed resistance. By shifting the electrochemical system closer to the diffusion-controlled regime and optimizing mass transport and electric field distribution, uniform deposition can be achieved with a thin seed layer and reduced overplating, thereby lowering overall process cost.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
This project applies Functional Modeling to analyze the single-wafer wet etch process in semiconductor manufacturing. The model shows that wet etch defects are not caused only by chemistry, but also by interactions between the wafer, liquid flow, air, rotation, rinsing, drying, drain, and chamber environment. Key challenges include incomplete wetting, trapped air or bubbles, residue and particle redeposition, evaporation-driven watermarks, and contamination during rinse or drying. The project identifies improvement directions such as better wafer pre-wetting, controlled airflow, reduced evaporation, optimized rinse and drying conditions, and alternative chamber concepts such as face-down processing in a shallow liquid bath.
Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage