Process: Cu-electroplating in semiconductor manufacturing
Problem: Non-uniform deposition - the thickness of the deposited Cu is high on the periphery of the wafer and decreases while moving to the central area of the wafer.
Current solutions: Deposit a thick layer of Cu and remove with polish (CMP), add a dummy cathode around the wafer to reduce the deposition at the periphery of the wafer.
Creative tools used: Problem statement analysis, 5Whys, Functional Modeling
Root cause found: The root cause is radial IR drop in the thin Cu seed layer, which causes spatial variation of local cathodic overpotential.
Fundamentals: The electrolysis process is described by the curve current vs voltage as shown on the chart:
There are two mechanisms of deposition:
As you can see, the Kinetic process strongly depends on the voltage - even a small variation of the voltage results in a big variation of the current, and results in a big variation of the deposited Cu - thikness.
The diffusion mechanism "keeps" the current stable versus the voltage variation.
The non-uniformity is amplified because the process operates predominantly in the kinetically controlled regime.
Correct Innovation Strategy
The objective is to reduce the sensitivity of deposition rate to local potential variations, rather than simply increasing seed thickness.
The strategic direction is:
Move the operating point closer to the diffusion-limited regime, where:
Current density ≈ limiting current
and becomes less sensitive to small voltage variations.
Proposed solutions:
To increase the rate of discharge of Cu-ions and reduce the diffusion of Cu-ions in the electrolyte.
Clean Final Strategic Statement:
The project does not aim to increase seed thickness or compensate for waste deposition. Instead, it aims to redesign operating conditions so that copper deposition becomes less sensitive to local voltage variations caused by seed resistance. By shifting the electrochemical system closer to the diffusion-controlled regime and optimizing mass transport and electric field distribution, uniform deposition can be achieved with a thin seed layer and reduced overplating, thereby lowering overall process cost.
This project investigates how to increase the copper removal rate during Chemical Mechanical Planarization (CMP). Functional modeling revealed that increasing H₂O₂ alone is ineffective beyond an optimum level because rapid oxidation creates a thick, passivating Cu₂O/CuO layer that must be mechanically removed. The winning direction is to balance faster oxidation with stronger mechanical removal by optimizing pad speed, abrasive concentration, pressure, conditioning, and slurry transport.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.