Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.

Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.