Found 10 projects in

Microelectronics

Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.

Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage

Copper electroplating is essential for forming advanced semiconductor interconnects, yet radial thickness non-uniformity remains a costly challenge. Thicker deposition at the wafer edge and thinner copper at the center force manufacturers to rely on overplating and CMP compensation, increasing material waste and process cost. Using the PRIZ Platform, this project reveals that the true amplification mechanism lies in operating within a kinetically controlled regime, where small voltage variations caused by seed-layer resistance produce large thickness deviations. By shifting the process closer to diffusion-controlled behavior and reducing sensitivity to voltage fluctuations, uniform deposition can be achieved intrinsically — enabling thinner seed layers, reduced overplating, lower CMP burden, and overall cost reduction.

The project was dedicated to production yield improvement in microchip manufacturing. The bumps are created on the top of a wafer and used for the final test of all dies. Only good dies are taken for the packaging. All dies that fail the test will be scrapped. The process yield depends on the amount of "good" and "bad" dies. It was revealed that in some cases, the time between the end of the process and the final test impacts the yield. The longer the dwelling, the more dies fail the final test. If the dwelling exceeds hundreds of hours, the amount of failed dies becomes dramatically high, which results in the scrapping of the whole wafer. The problem was analyzed and solved.

The number of particles is a critical parameter for microchip manufacturing. Each, even a very small particle, can potentially destroy a die. Therefore filters are widely used. Water is always filtered through fine filters to reduce the number of particles. Nevertheless, if the filter is too fine, it could cause a problem. This issue was investigated with the help of Functional Modeling. Possible solutions were generated using 40 Inventive Principles.